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IEEE International Symposium on
Defect and Fault Tolerance in VLSI and Nanotechnology
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CALL FOR PAPERS
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DFT is an annual Symposium providing an open forum for presentations in the field of defect and fault tolerance in VLSI and nanotechnology systems inclusive of emerging technologies. One of the unique features of this symposium is to combine new academic research with state-of-the-art industrial data, necessary ingredients for significant advances in this field. All aspects of design, manufacturing, test, reliability, and availability that are affected by defects during manufacturing and by faults during system operation are of interest. The topics include (but are not limited to) the following ones: 1. Yield Analysis and Modeling: Defect/fault analysis and models; statistical yield modeling; diagnosis; critical area and other metrics. 2. Testing Techniques: Built-in self-test; delay fault modeling and diagnosis; testing for analog and mixed circuits; online testing; signal and clock integrity. 3. Design For Testability in IC Design: FPGA, SoC, NoC, ASIC, low power design and microprocessors. 4. Error Detection, Correction, and Recovery: Self-testing and self-checking solutions; error-control coding; fault masking and avoidance; recovery schemes, space/time redundancy; hw/sw techniques; architectural-specific techniques, system-level design-time or runtime strategies. 5. Dependability Analysis and Validation: Fault injection techniques and frameworks; dependability and characterization. 6. Repair, Restructuring and Reconfiguration: Repairable logic; reconfigurable circuit design; DFT for on-line operation; self-healing; reliable FPGA-based systems. 7. Design for Defect and Fault Tolerance: Reliable circuit/system synthesis; radiation hardened and/or tolerant processes and design; design space exploration for dependable systems, transient/soft faults and errors. 8. Aging and Lifetime Reliability: Aging characterization and modeling; design and run-time reliability, thermal, and variability management and recovery. 9. Dependable Applications and Case Studies: Methodologies and case study applications to Internet of Things, automotive, railway, avionics and space, autonomous systems, industrial control, etc. 10. Emerging Technologies: Techniques for 2.5D/3D ICs, quantum computing architectures, microfluid biochips, etc. 11. Design for Security: Fault attacks, fault tolerance-based countermeasures, hw security assurance, hw trojans, resistance to persistent DoS, security vs. reliability trade-offs, interaction between VLSI test, trust, and reliability. |
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Prospective authors are invited to submit original and unpublished contributions. Two types of submissions are possible: (i) regular papers (6 pages), and (ii) short papers (4 pages). Both types will be included in the symposium proceedings and should adhere to the IEEE conference template, 2-columns style (available on conference web site), and submitted as PDF file, electronically. Detailed information about the submission process are available on the symposium website. Proposals for special sessions are also invited this year. For more information, visit symposium website. |
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Paper submission deadline: Apr 28, 2017 Notification of acceptance: July 1, 2017 Camera ready and author's registration: July 21, 2017 |
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Awards All papers will be considered for the DFT 2017 Best Paper Award. A best Student Paper Award (funded by Cadence) will be assigned to the best paper having a student as first author Organization General co-chairs:
Program co-chairs:
Industrial liaison chair:
Publicity chairs:
Publication chair:
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Program Committee
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For more information, visit
us on the web at: http://www.dfts.org/
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The CONFERENCE is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC). |
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IEEE Computer Society- Test
Technology Technical Council
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